The present invention relates generally to the electrical, electronic and computer arts, and, more particularly, to integrated circuit (IC) interconnects.
Three-dimensional (3D) chip stacking relies on metallized interconnect structures between silicon layers to enable electrical communication between the respective chips. Chip stacking, as the name suggests, refers to an IC packaging methodology in which a completed computer chip (e.g., dynamic random access memory (DRAM)) is placed on top of another chip (e.g., a central processing unit (CPU)). As a result, two chips that were traditionally centimeters apart on a circuit board are now less than a millimeter apart. This reduces power consumption and also improves bandwidth by a significant amount.
Although several options exist for making 3D interconnect structures, soldering remains one of the most popular. However, plating, evaporation or other solder deposition methods are typically expensive and complex and limit the alloys that may be used. Additionally, conventional solder deposition methods produce a spacing between adjacent chips, referred to herein as standoff height, which substantially increases the overall package height of the chip stack and furthermore is not sufficient for high-frequency signals. The shorter interconnect wires will decrease both the average parasitic load capacitance and the resistance. Also there is a demand to make the total stacked package height as low as possible in a mobile application industry market.